Accompanying the introduction of higher integration and higher performance of LSIs (semiconductor devices), the miniaturization of a MISFET constituting an LSI has been advanced. As a gate length of the MISFET is scaled, a problem of short channel effect that reduces a threshold voltage Vth has become significant. This short channel effect arises from the fact that the broadening of depletion layers of the source and drain portions of the MISFET affects up to a channel portion along with the miniaturization of the channel length.
However, in recent years, a full depletion type SOI structure has been attracting attentions. In this structure, the depletion layer induced in a body region directly below a gate electrode reaches up to the bottom of the body region, that is, an interface of the body region and a buried insulating layer, and thus a steep sub-threshold factor (S-factor) is obtained. In general, with respect to an element having a gate length smaller than or equal to 100 nm, a thin single-crystal semiconductor layer (SOI layer) on the buried insulating layer is required to be smaller than or equal to 20 nm.
At this time, since a diffusion layer (semiconductor region) constituting the source and drain is also formed inside the thin SOI layer, an external resistance of the MISFET becomes high. Further, when a silicide layer is formed on an upper portion of the diffusion layer to reduce the resistance, a silicide layer reaches up to the buried insulating layer, and this reduces a contact area between the diffusion layer and the silicide layer, and a problem arises that a contact resistance is increased and a current is reduced.
To avoid these problems, it is conceivable to form a so-called elevated source and drain structure (hereinafter, the stacked semiconductor layers are referred to as an elevated layer), which constitutes the source and drain by the semiconductor layers elevated at both sides of the gate (gate electrode). This is because, by elevating, that is, stacking semiconductor layers on the SOI layer serving as a base by using a selective epitaxial growth method, the silicide layer is prevented from reaching up to the buried insulating layer and the external resistance of the MISFET can be reduced.
Meanwhile, since a breakdown voltage between source and drain of the MISFET fabricated on the SOI substrate is deteriorated, there arises a problem that it can be used only in a low voltage regime. Hence, it is desirable that a high-breakdown voltage element (for example, MISFET), and an ESD (electrostatic breakdown) protection element and the like for preventing ESD are fabricated not on the SOI substrate, but on a bulk substrate.
In Hou-Yu Chen et al., “Novel 20 nm Hybrid SOI/Bulk CMOS Technology with 0.183 μm2 6T-SRAM Cell by Immersion Lithography”, 2005 Symposium on VLSI Technology Digest of Technical Papers, 2005, pp. 16-17 (Non-Patent Document 1), the SOI layer and the elevated insulating layer of the SOI substrate are removed, so that a bulk region whose silicon substrate is exposed on the same substrate is formed. As a result, by using the SOI substrate having an extremely thin buried insulating layer having a 20-nm thickness so that a step between the bulk region and the SOI region is made low, the SOI region can be formed with the MISFET (hereinafter, referred to as SOI-MISFET) and the bulk region can be formed with the MISFET (hereinafter, referred to as bulk-MISFET) by a common process without further complication.